On Chip Networks and teraflop computing

Last week in a keynote at IDF in bangalore, Intel’s senior fellow Kevin Kahn had a designer from Intel’s India Development centre come up on the stage and show a shining new wafer containing an experimental teraflop programmable processor with 80 cores on the chip. EETimes has more detail:

Each tile includes a small core, or compute element, with a simple instruction set for processing floating-point data,…

The tile also includes a router connecting the core to an on-chip network that links all the cores to each other and gives them access to memory. The second major part is a 20-Mbyte SRAM memory chip that is stacked on and bonded to the processor die. Stacking the die makes possible thousands of interconnects and provides more than a terabyte-per-second of bandwidth between memory and the cores…

“When combined with our recent breakthroughs in silicon photonics, these experimental chips address the three major requirements for terascale computing—Tflops of performance, terabytes-per-second of memory bandwidth, and terabits-per-second of I/O capacity,”…

One of the key challanges faced, as briefly mentioned at the IDF here, was a need for them to come up with an interconnection fabric. This PDF at Intel’s site has some graphical representation of such interconnects and some more information. A few interesting problems arise at such scale of computing, the bibliography at the On-Chip Network resource page seems like a good place to explore more.

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